1. Field
Example embodiments relate to a non-volatile memory device with interspersed or separately arranged flag cells in multi-level memory cells and a method for operating the memory device.
2. Description of the Related Art
Related art non-volatile memory devices may include a NAND flash memory and a NOR flash memory. NOR flash memory may exhibit faster characteristic access time because each of its memory cells is independently connected to a bit line and a word line. The NAND flash memory may possess superior integration because of its string structure, in which a plurality of memory cells are serially connected. NAND flash memory may be used for a high capacity flash memory in digital cameras or PC cards, instead of hard disks.
FIG. 1 is a block diagram showing the arrangement of a cell array of a related art non-volatile memory. In FIG. 1, a non-volatile memory 100 may include a memory cell array 110, a flag cell array 120, a row decoder 130, and/or a page buffer 140. The memory cell array 110 may include a plurality of multi-level memory cells capable of storing data in multi-bit form.
The flag cell array 120 may include a plurality of flag cells 121 through 124, each of which may indicate whether its corresponding memory cells are MSB (most significant bit) programmed. The memory cells and the flag cells may be arranged in a matrix including a plurality of rows and columns.
FIG. 2 is a circuit diagram of the cells of the related art non-volatile memory 100 arranged in a plurality of rows and columns. The related art non-volatile memory 100 shown in FIG. 2 is a NAND flash memory. As shown in FIG. 2, the cells of the respective rows of the related art non-volatile memory 100 may be connected to the same word lines WL0-WLm, while the cells of the respective columns may be connected to the same bit lines BL0-BLn.
The row decoder 130 may be connected to a string selection line (SSL), a plurality of word lines WL0-WLm, and a ground selection line (GSL). The row decoder 130 may select a word line based on a combination of a memory block at a given address and a word line from a selected string. The page buffer 140 may be connected to a plurality of bit lines BL0-BLn and may buffer data to be input to or output from a selected row.
In FIG. 1, the flag cell array 120 of the related art non-volatile memory 100 may be densely arranged entirely to one side of the memory cell array 110. If any cell in a flag cell array is damaged and/or has a defect (for example, a large particle falls on a cell) all flag cells may not operate normally. In this case, increased errors may occur while data is read out of the memory cells, depending on whether the MSB program is performed. It is a further problem that, during this event, no cells of the non-volatile memory may be used.